1. Field of the Invention
The present invention relates to an insulated gate bipolar transistor and a method of fabricating the same.
2. Description of the Related Art
An insulated gate bipolar transistor (hereinafter referred to as IGBT) has high input impedance of a field effect transistor and a high current drive capability of a bipolar transistor, and is particularly suitable for use as a power switching device.
An IGBT has such a problem that as the density of current flowing through the device increases, the parasitic thyristor is turned on so that the device is likely to go to a latch-up state in which case the device may be broken. To suppress the occurrence of the latch-up, a device with a buffer region is developed as disclosed in Unexamined Japanese Patent Application KOKAI Publication No. H5-55583.
The conventional IGBT with a buffer region has a semiconductor substrate, a collector electrode, an emitter electrode, a gate insulating layer, and a gate electrode. The semiconductor substrate includes a P-type collector region, an N+-type buffer region having a relatively high impurity concentration formed on the collector region, an N-type base region having a relatively low impurity concentration formed on the buffer region, a P-type base region provided like lands in the surface region of the N-type base region, and an N-type emitter region provided like lands in the surface region of the P-type base region.
The collector electrode is electrically connected to the collector region. The emitter electrode is electrically connected to the emitter region. The gate electrode is formed on the P-type base region, sandwiched between the N-type base region and the emitter region, via the gate insulating layer.
In the IGBT, the buffer region has a capability of optimizing (suppressing) the amount of holes to be injected into the N-type base region from the collector region and preventing the latch-up. When the N-type base region is formed directly on the collector region with no buffer region formed, more than necessary holes are injected into the N-type base region from the collector region, making the occurrence of the latch-up easier. The buffer region suppresses the latch-up and improves the reliability of the device.
The IGBT with the buffer region however has a problem such that the so-called tail current is large so that the switching speed is apt to become slower. This seems to be attributed to the following reason. When the device is turned off with the voltage to be applied to the gate electrode being set equal to or lower than a threshold voltage Vth, the PN junction formed at the interface between the N-type base region and the P-type base region is reverse-biased, causing the depletion layer to extend into the N-type base region from the PN junction. At this time, minority carriers (holes) stored in the N-type base region are discharged via the P-type base region. As the depletion layer does not substantially extend into the buffer region, however, the carriers stored in the buffer region are not discharged. Accordingly, the current (tail current) keeps flowing until the minority carriers stored in the buffer region are recombined. As a result, the switching speed of the IGBT becomes slower.
The buffer region of the IGBT is generally formed of phosphorus. As phosphorus is likely to be diffused into the semiconductor region, however, the phosphorus in the buffer region may be diffused into the N-type base region by the heat generated in the fabrication process of the semiconductor device. When the device is completed as an IGBT, therefore, the buffer region is formed thick with a relatively low impurity concentration. Consequently, the completed IGBT becomes more likely to store holes in the buffer region and takes a longer time to get the holes recombined to vanish, allowing the tail current to be large.
One way to solve the problem is to form the buffer region thin beforehand in consideration of heat-originated diffusion. In this case, however, the impurity concentration of the buffer region should be made higher. This results in sharp concentration gradient with respect to another adjoining layer, causing diffusion of a greater amount of phosphorus. Therefore, the buffer region eventually becomes thick and the impurity concentration cannot be increased sufficiently. In other words, the problem that the tail current is likely to become large is not solved.
On the other hand, there are methods for applying electron irradiation, heavy metal diffusion, or the like, for decreasing the tail current. However, these methods cause defects inside the device, which leads to degradation of device characteristics, such as increase in collector-emitter voltage VCE (sat), which is a critical characteristic of an IGBT, decrease in threshold voltage Vth, and increase in leak current when a reverse voltage is applied between the collector and the emitter. These methods cause not only such degradation of device characteristics, but also other bad effects such as large change in device characteristics at a high working temperature. Furthermore, these methods give rise to a problem that the frequency of occurrence of switching loss is greatly increased during device operation at a high temperature.
In view of the situation, the present inventors have developed a scheme of forming a buffer region using arsenic (As) as a donor impurity as disclosed in a copending Japanese patent application filed at the Japanese Patent Office and not published yet. According to the scheme, the use of arsenic having a diffusion coefficient lower by about one figure than that of phosphorus can increase the impurity concentration of the buffer region (5×1017 cm−3 or higher) and make the buffer region thinner (2 to 10 μm). This can reduce the amount of carriers to be stored in the buffer region and can thus reduce the tail current. That is, forming the buffer region containing arsenic at a relatively high concentration relatively thick achieves a device which has a reduced tail current, thereby improving the speed, and adequately prevents the latch-up.
When the buffer region containing arsenic as a donor impurity was formed on the collector region containing boron as an acceptor impurity after which a device fabrication process such as formation of an N-type base region or so was performed according to the scheme, however, there was a phenomenon observed in which boron in the collector region was diffused over the buffer region into the N-type base region. After device fabrication, the diffusion of boron over the buffer region changes the impurity concentration in the N-type base region.
This phenomenon occurs for the diffusion coefficient of boron is greater by about one figure than that of arsenic. As boron in the collector region is diffused over the buffer region into the N-type base region, the breakdown voltage characteristic follows the channel pattern undesirably. The channel pattern is the phenomenon that the leak current becomes greater when a relatively low reverse voltage is applied. When the breakdown voltage characteristic follows the channel pattern, the breakdown voltage distribution becomes non-uniform, bringing about a reduction in breakdown voltage which would impair the reliability of the device.
As mentioned above, an IGBT having a buffer region containing arsenic can achieve a high switching speed and a good latch-up resistance. When the diffusivity of the impurity contained in the collector region is high, however, the breakdown voltage drops as the impurity is diffused over the relatively thin buffer region, which may impair the reliability of the device.